Pardon my naivete, but it seems to me that drilling a hole through silicon and filling it with copper is just creating a "short" through the wafer. I think they mean to surround the copper with a dielectric. But then we all know what this means. You now have a MOS capacitor running through the wafer. I think the signal integrity between wafers will be ridiculous at high frequencies.

Hi PG,
I'm not sure what you're referring to, specifically, but, vias are meant to be shorts. You only via what you want grounded to the bottom surface.
One of the biggest reasons we used vias was for better performance at higher freq's. If you were to use the usual surface ribbon metal (3 mil, say) between the grounds of each component of say a 5 x 100 um PHEMT, you would add a great deal of parasitics to each of the 100um cells, where individual Source vias (ISV) would decrease your Source inductance (Impedance) directly reducing your gain (Rd/Rs).
Make sense?
Peace,
Ron

Ron, thanks for your note, maybe I misunderstood the originally intended application. -p.g.

These vias have been made historically in GaAs and other III-V compounds, where you naturally get an insulating Schottky barrier from any metal-semiconductor contact unless you have active measures to prevent it.

And anyway, it served in microwave chips where GaAs is chosen semi-insulating to reduce stray capacitances (and to allow making inductors), so a contact wouldn't be a big drawback. It might inject carriers, but deep dopant levels would just store these carriers.

Bye!