http://www.physorg.com/news89109741.html

A big change to high-k and metal gate, but only 20% boost in performance?! Dynamic voltage reduction and resistance to supply rail goes a long way.

Gate leakage is not a big issue for every transistor only those transistors that are connected to ground (furthest from Vdd) and are then turned on. A 1V signal say applied to the gate can drive tunneling through the oxide to the channel which is effectively ground. If the channel is at a higher voltage, closer to 1V, the leakage current through the oxide is reduced exponentially. Transistor stack design has a lot of possibilities to reduce leakage. On the other hand, high-k material choice is subject to lots of constraints (like process and interface quality) which limit the number of choices to a few transition metal oxides or silicates.

When a TaN gate is used on top of a HfO2 gate dielectric, the Ta diffuses through the HfO2, resulting in trap states that degrade the mobility. I would imagine this is a prevalent concern.

Where did they publish this? Or was it just a press release?

Appl. Phys. Lett. 86, 012901 (2005)

Effects of tantalum penetration through hafnium oxide layer on carrier generation rate in silicon substrate and carrier mobility degradation
Chang Yong Kang, Se Jong Rhee, Chang Hwan Choi, M. S. Akvar, Manhong Zhang, Taekhwi Lee, Injo Ok, and Jack C. Lee
Microelectronics Research Center, R9950, The University of Texas at Austin, Austin, Texas 78758

(Received 10 September 2004; accepted 15 November 2004; published online 23 December 2004)

This letter presents the effects of tantalum penetration through hafnium oxide on bulk carrier generation rates and carrier mobility degradation. The penetration of Ta atoms degraded the bulk carrier lifetime in the Si substrate. Surface nitrogen incorporation can be useful to mitigate Ta penetration into the Si substrate. The incorporated Ta in the dielectric was found to have no effect on the effective value. On the other hand, it increased pre-existing traps and interface states. Thus, mobility degradation for tantalum nitride gate devices was primarily caused by pre-existing traps and interface states of the high-k dielectrics. ©2005 American Institute of Physics

I heard even if you deposited HfO2 on Si, an interface layer of HfSiO would form and further that the interface between this HfSiO layer and the Si is just like original silicon dioxide. Hence, you still have thin silicon oxide under the high-k layer, with interfacial layer in between. So the dielectric constant is not as high as you would expect from HfO2.

You can get >10X gate leakage reduction already using silicon nitride film with silicon oxide. The dielectric constant ~ 7.5 allows you to control EOT (~thickness/dielectric constant) more effectively as well.