http://www.physorg.com/news7540.html

This article sports too naive a perspective. The Japanese have tried to tackle this years ago. A key problem is inevitable contamination deposition. This will clearly be a strong concern with the desired surface reactions going on here.

Etching right inside the E beam chamber seems like it would cause a lot of contamination. I don't think the dimensions they claim will actually be achieved.

I had developed a code impervious to even quantum computers. The algorithm is a little slow though. Is that worth anything?

slevak wrote:
>> I had developed a code impervious to even quantum computers. The algorithm is a little slow
>> though. Is that worth anything?


yes - email it to me! h4rh4rh4r@hotmail.com

Aren't chips on silicon wafers today alread being made using electron beam lithography? Otherwise how can they be so small?

Electron beam lithography is too slow to be used to produce lots of wafers. Only Intel would be able to buy 1000 electron beam tools for each of its optical tools, to match the output rate. Optical lithography is still the way it is done.

ll, you wrote:



Can't electron beam lithography be used for just the smallest features, optical for everything else?

Mix-and-match is used in low volume demonstrations. But using the electron beam writing in large volume in this way is still not likely, for two reasons.

First, the "smallest features" are likely everywhere in the chip. Second, the electron beam with its fine resolution at each point takes such a long time to write, the delay for a single wafer would be intolerable.

There is ongoing work by several groups on using multiple electron beams to do more writing in parallel. The energies are generally much lower than the traditional electron beam lithography tool, like 1-2 keV instead of 50-100 keV. So the resolution advantage may be harder to attain.