Nanoimprint lithography has seen impressive progress in the past year. In addition, one semiconductor company (Toshiba) and one semiconductor equipment company (Canon) have virtually given their endorsement. Plus there have been supporting reviews from Samsung and even activity from NIST. But there is more to nanoimprint acceptability than just successful demos and good reviews. The infrastructure is needed, such as template fabrication, inspection, and imprint materials. Plus, defect and throughput and overlay and layout requirements need to be compared with the incumbent lithography.
There is an infrastructure problem regarding the diversity of stamps.
For example, Molecular Imprints uses small size template, 65 mm X 65 mm, made from fused silica. On the other hand, Obducat uses full wafer imprint, with wafer sizes currently up to 8".
It seems redundant to support both platforms.
For example, Molecular Imprints uses small size template, 65 mm X 65 mm, made from fused silica. On the other hand, Obducat uses full wafer imprint, with wafer sizes currently up to 8".
It seems redundant to support both platforms.
Bubble defects when nanoimprint not in vacuum. Vacuum kills throughput.
I actualy vote for litography limit 11-16 nm, somthing about 55-80 atoms. It's hard to believe that transistors can be such thicknes and even if can, then isolators, connections, etc still will take major place and effiecency and speed of processors will alsmost not increase. But I think that it never be used. I am very sceptical about farther developing of processors and lithorgraphy... Heisenber uncertainty principle gonna get you... 
QUOTE (DavidD+May 17 2008, 06:54 PM)
It's hard to believe that transistors can be such thicknes
- Not so mind-quakingly para-incredulous as the apparent thickness you seem to possess.
- Not so mind-quakingly para-incredulous as the apparent thickness you seem to possess.
Now if they only had done this when people were still using contact aligners. 
Seriously, the only thing I can see it conveniently doing for ICs is 3D stuff, like TSVs and such. It goes along with the wafer bonding and stacking scheme, which is based on intimate contact. That might pull in the timeline (it would become independent of which node, etc.) since stacking is already done today.
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