The resolution of printing small features by lithography is quickly
approaching the limits of acid diffusion and graininess within resists.
http://www.future-fab.com/documents.asp?grID=213&d_ID=2614
It seems that before the end of the decade we need to seriously think
about how to achieve manufacturable nanopatterning.
Or just admit that something in the 40 nm range is as far as ICs are
going to go, Moore's Law has at last hit the wall, and who needs 100
billion transistors on a chip anyhow?
John
going to go, Moore's Law has at last hit the wall, and who needs 100
billion transistors on a chip anyhow?
John
The admission that it is as far as we can go would go against what makes us human...the drive to progress and "self-evolve" if you will. 
Well said.
Folks, it isn't lithography that's hitting the wall, it's all the quantum effects that are causing problems. I agree, traditional lithography is done at 45nm, but once we switch to EUV lithography, the limitations of quantum physics far outweigh any limitations in lithography.
this is why i believe jmar technologies will be worthwhile in owning as of today. Euv technolgy is here and tested. cheers morten
I for one am really, really looking forward to EUV. Since it uses 13.4nm light (as opposed to 193 or even 248nm), the only limitation to feature size is going to be how good the mirrors and the quality of the masks are. It will eliminate the need for costly procedures like hyper-numerical aperature, full immersion lithography, etc.
The admission that it is as far as we can go would go against what makes us human...the drive to progress and "self-evolve" if you will.
Youd really hate to live in the very far future where we definately know everything then
Youd really hate to live in the very far future where we definately know everything then
And who needs 100 billion transistors on a chip anyhow?
Hmmm i dont think you can get 100 billion transistors on a average sized chip we have in our computers today on a 22nm process...
Saying that-22NM process will get us extremely powerful processors, this processing power wont really be needed for a singular program everyone needs or uses, the only uses i can think for processors like this are for major fast servers and space calculations for when they make observations, and as (forgot its name) that company does, you sign your computer up and whenever youre online it uses your processor to help process all the information, that is what the future will primarily be about, everyone online sharing each other processing power so you can theoretically when you need it have 200 massive processor helping you do something when theyre not being used by someone else without having a 400ft tower in your computer room.
Personally that is the way forward as there will always be a limit to power, with this idea you can get that same power, and while it takes the same space-it isnt all in one tower you would have trouble fitting into a room with.
Even with quantumn computers there will be a limit, in the end if anything does need more processing power than the very best can perform-this way i have presented (which isnt exactly new but is ignored quite a lot) is the best way forward, unfortunately the only drawback i can think of is that you would need an internet connection that can send back the information needed at a fast enough speed, or a processor with enough cache to store the memory on and send it in packets.
Either way they always find a way forward
Hmmm i dont think you can get 100 billion transistors on a average sized chip we have in our computers today on a 22nm process...
Saying that-22NM process will get us extremely powerful processors, this processing power wont really be needed for a singular program everyone needs or uses, the only uses i can think for processors like this are for major fast servers and space calculations for when they make observations, and as (forgot its name) that company does, you sign your computer up and whenever youre online it uses your processor to help process all the information, that is what the future will primarily be about, everyone online sharing each other processing power so you can theoretically when you need it have 200 massive processor helping you do something when theyre not being used by someone else without having a 400ft tower in your computer room.
Personally that is the way forward as there will always be a limit to power, with this idea you can get that same power, and while it takes the same space-it isnt all in one tower you would have trouble fitting into a room with.
Even with quantumn computers there will be a limit, in the end if anything does need more processing power than the very best can perform-this way i have presented (which isnt exactly new but is ignored quite a lot) is the best way forward, unfortunately the only drawback i can think of is that you would need an internet connection that can send back the information needed at a fast enough speed, or a processor with enough cache to store the memory on and send it in packets.
Either way they always find a way forward
Problem with EUV is the light source. Rather than a laser or a gas lamp, a plasma is used. The plasma particles bombard the optics, damaging them in the process. 
After thinking about this quite a bit, it seems to me (almost pretty obvious now) that the way to go would be multiple DUV (248 nm) expose-and-etch steps with a maskless tool, using positive and negative photoresists. If this goes too slow then this sequence can be used to make a nanoimprint mask, which can then be used for mass production.
This way, no need to fret about electron-beam, EUV or immersion. The technology is already here.
It is important to consider simple lithographic solutions, especially since other issues loom for the nodes ahead, like high-k, metal gates, interconnects, FD-SOI, etc.
This way, no need to fret about electron-beam, EUV or immersion. The technology is already here.
It is important to consider simple lithographic solutions, especially since other issues loom for the nodes ahead, like high-k, metal gates, interconnects, FD-SOI, etc.
As this original post is quite old, I would like to present some info that everyone may or may not be aware of. In June a group from the University of Alberta published in nature their invention of a single molecule transistor operated at room temperature controled by a single charged atom. This is an improvement over other groups single molecule transistors which were operated at very cold temperatures (4K if I remember correctly) and needed large contacts with an applied voltage to control switching. With this new transistor, the current is a single electron, which would all many more transistors on a single chip because there will be much less heat. This of course is not that simple, and there is an estimate of approximately 10 years by this group until this new invention will produce anything applicable, but is exciting none the less.
Also, there has been a lot of interesting work done with carbon nanotubes, and they are even now growing them in a Y shape which might be able to be used as a transistor also. So there may be new processor technology that doesn't rely on lowering the limits of optical lithography.
I have read about 'soft lithography' which is basically a stamp, with 'ink' on it. The limits of this kind of lithography are supposed to be on the order of 1 nanometer. Also I have read about using AFM tips that are designed like a fountain pen to write out patterns this way, although this would be a very slow process I think.
I also think its possible for E-beam to be a viable possibility for lithography. I was taking a course on E-beam, and the instructor suggested a possibility to solve several of the problems with e-beam (its speed, and being able to use smaller currents) might be solved by using traditional ebeam to make masks, and then using a large, low voltage electron source instead of UV light. I don't know if this idea will ever be used, but it seems like a possibility at least.
Anyways, I hope for nanoproccessors with single molecule transistors.
Also, there has been a lot of interesting work done with carbon nanotubes, and they are even now growing them in a Y shape which might be able to be used as a transistor also. So there may be new processor technology that doesn't rely on lowering the limits of optical lithography.
I have read about 'soft lithography' which is basically a stamp, with 'ink' on it. The limits of this kind of lithography are supposed to be on the order of 1 nanometer. Also I have read about using AFM tips that are designed like a fountain pen to write out patterns this way, although this would be a very slow process I think.
I also think its possible for E-beam to be a viable possibility for lithography. I was taking a course on E-beam, and the instructor suggested a possibility to solve several of the problems with e-beam (its speed, and being able to use smaller currents) might be solved by using traditional ebeam to make masks, and then using a large, low voltage electron source instead of UV light. I don't know if this idea will ever be used, but it seems like a possibility at least.
Anyways, I hope for nanoproccessors with single molecule transistors.
QUOTE
SteveO: I have read about 'soft lithography' which is basically a stamp, with 'ink' on it.
I read about that too. That's a form of nanoimprint lithography. Nanoimprint 'masks' are actually stamps or templates. These techniques are quite cheap and already have been used in some niche areas.
QUOTE (->
| QUOTE |
| SteveO: I have read about 'soft lithography' which is basically a stamp, with 'ink' on it. |
I read about that too. That's a form of nanoimprint lithography. Nanoimprint 'masks' are actually stamps or templates. These techniques are quite cheap and already have been used in some niche areas.
SteveO: I also think its possible for E-beam to be a viable possibility for lithography. I was taking a course on E-beam, and the instructor suggested a possibility to solve several of the problems with e-beam (its speed, and being able to use smaller currents) might be solved by using traditional ebeam to make masks, and then using a large, low voltage electron source instead of UV light. I don't know if this idea will ever be used, but it seems like a possibility at least.
I think it's called LEEPL and is developed mainly in Japan.
One thing to be careful of is secondary radiation (i.e., electrons) generated by primary radiation that is energetic enough to be ionizing (e.g., EUV, X-ray, electrons). This secondary radiation does most of the resist exposure, actually.
DUV light is not ionizing, but cannot put up the resolution without a lot of wrangling, such as resolution enhancements, multiple exposures, immersion. So if this is too costly or time-consuming, maybe making a limited number of imprint templates is more worthwhile.
There is also the possibility of arrayed STM or AFM, which is probably what Dip Pen is all about, but their resolution depends on the tip and other conditions.
Anyway, it's the final product that is really what matters. These are interesting times indeed, with single-electron and single-molecule devices arriving well ahead of lithography techniques!
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I think it's called LEEPL and is developed mainly in Japan.
That is interesting, I was completely unaware of that!
QUOTE (->
| QUOTE |
| I think it's called LEEPL and is developed mainly in Japan. |
That is interesting, I was completely unaware of that!
One thing to be careful of is secondary radiation (i.e., electrons) generated by primary radiation that is energetic enough to be ionizing (e.g., EUV, X-ray, electrons). This secondary radiation does most of the resist exposure, actually.
Thats exactly why the instructer for my EBL course suggested that possiblity, because you could use less energetic electrons with a lower voltage, and have less secondary radiation. Where I work uses the Raith 150, and it has a range of voltages from I think 0.1keV to 30keV. We usually operate at about 20keV, but it would be great if you could use a mask and have way less energetic electrons.
Apparently in germany with the Rith 150 they have got features down to 6nm in size, which isn't to bad at all.
Maybe there will be some lithographic revolution and it will catch up and be able to produce sub nanometer sizes, depending on the material being used. (if a molecule is larger than a nanometer you couldn't make sub nanometer features of course)
Hi Steveo,
I can't agree more. Naval Research Labs has used STM with really low voltages to expose resists. These low energy electrons go surprisingly far (tens of nanometers). These are the same energy as the usual secondary electrons which expose resist.
I am aware people have published sub-10 nm results but how repeatable can this be? Raith only guarantees down to 20 nm. If you do Monte Carlo simulations you can see how random and noisy these electrons really are.
Using DUV optical maskless (like Sigma 7300) to make a nanoimprint template still seems like the best bet for now for the long term. I would expose and etch a negative photoresist like SU8 many times for example. Sigma 7300 is also way faster than the electron beam tools.
QUOTE
...you could use less energetic electrons with a lower voltage, and have less secondary radiation
I can't agree more. Naval Research Labs has used STM with really low voltages to expose resists. These low energy electrons go surprisingly far (tens of nanometers). These are the same energy as the usual secondary electrons which expose resist.
I am aware people have published sub-10 nm results but how repeatable can this be? Raith only guarantees down to 20 nm. If you do Monte Carlo simulations you can see how random and noisy these electrons really are.
Using DUV optical maskless (like Sigma 7300) to make a nanoimprint template still seems like the best bet for now for the long term. I would expose and etch a negative photoresist like SU8 many times for example. Sigma 7300 is also way faster than the electron beam tools.
Your right, E-beam tools aren't the fastest, although from the info I have given is that some of the expensive, commerical ebeam systems can do small features very quickly.
Your right, the 6nm features probably aren't very repeatable, although even 25nm (on the Raith we have at my lab) isn't all that repeatable (because of crappy vibration insulation at the facility I am at.
I have only started in micro and nanofabrication in the last few months, so I am still a newbie at it.
Your right, the 6nm features probably aren't very repeatable, although even 25nm (on the Raith we have at my lab) isn't all that repeatable (because of crappy vibration insulation at the facility I am at.
I have only started in micro and nanofabrication in the last few months, so I am still a newbie at it.
Immersion makes 45 nm already possible. The "32 nm node" is commonly held to be 90-110 nm pitch anyway, a little less than half of today's design rules, but achievable with ASML's 1700i tool, for example . So this definitely buys the industry time.
Quote: "who needs 100 billion transistors on a chip anyhow?"
Windows 98 was written with the assumption that nobody would need more than 128 megs of ram, and slows down with more than 160 megs, and becomes unstable with more than 192 megs. Ye olde DOS made the assumption that nobody would ever need more than 640K ram. A decade or so earlier, it was stated by an expert that nobody would ever need more than 16K of memory.
The above quote will seem silly sooner that you might think.
Windows 98 was written with the assumption that nobody would need more than 128 megs of ram, and slows down with more than 160 megs, and becomes unstable with more than 192 megs. Ye olde DOS made the assumption that nobody would ever need more than 640K ram. A decade or so earlier, it was stated by an expert that nobody would ever need more than 16K of memory.
The above quote will seem silly sooner that you might think.
QUOTE
Immersion makes 45 nm already possible. The "32 nm node" is commonly held to be 90-110 nm pitch anyway, a little less than half of today's design rules, but achievable with ASML's 1700i tool, for example . So this definitely buys the industry time.
I was looking for the price tag of this tool (ASML 1700i). Sometimes such a figure is published online. Nikon's NSR-S609B is around $35 million, with an NA of 1.07 and throughput of 130 WPH.
QUOTE
I was looking for the price tag of this tool (ASML 1700i). Sometimes such a figure is published online. Nikon's NSR-S609B is around $35 million, with an NA of 1.07 and throughput of 130 WPH.
Actually I was surprised to find the cost published online. Usually, you read about it in interviews with executives complaining about the higher costs.
What is happening is as resolution requirements become finer, the CoO for maintaining the same throughput is growing rapidly.
The higher cost comes from more higher-quality optical components required, new materials, contamination maintenance, resolution enhancements, etc.
At the same time, it is harder to maintain the same throughput as resolution becomes finer, for a variety of reasons. Acid diffusion and line-edge roughness (the topic of the original post) are two of them. Multiple-exposure strategies are already being contemplated for the latest optical lithography tools. There is also shot noise for higher-energy quanta (like EUV/X-ray photons or electrons), which could worsen throughput.
Eventually tighter resolution requirements will make it impossible to continue this trend using these tools anyway. Only nanoimprint will survive at that point.
All the more reasons to break out of this trend early.
The way line-edge roughness is affected by shot noise is this:
Typically we expect to have:
EUV dose = 5 mJ/cm^2: 14 photons in a 2 nm square
ArF dose = 25 mJ/cm^2: 240 photons in a 2 nm square
The Poisson statistics show 3s/avg = 3*sqrt(14)/14 = 81% for EUV
= 3*sqrt(240)/240 = 10% for ArF
Such large uncertainty means one can have 2 nm pixels which are randomly unexposed. At the feature edge where dose falls off, this effect is aggravated. This is also much worse for EUV than for ArF or DUV because fewer photons are used for exposure. This is the dose contribution to LER. It is a natural variation in the exposure dose.
For chemically amplified resists, each photon ultimately generates lots of acids. The acid number has much less shot noise but at the cost of resolution (more blur), since these acids have to diffuse.
For ionizing radiation, as I mentioned elsewhere, each EUV or X-ray photon generates an avalanche of electrons which in turn can diffuse and generate more acids which also diffuse. These two factors increase blur significantly.
Typically we expect to have:
EUV dose = 5 mJ/cm^2: 14 photons in a 2 nm square
ArF dose = 25 mJ/cm^2: 240 photons in a 2 nm square
The Poisson statistics show 3s/avg = 3*sqrt(14)/14 = 81% for EUV
= 3*sqrt(240)/240 = 10% for ArF
Such large uncertainty means one can have 2 nm pixels which are randomly unexposed. At the feature edge where dose falls off, this effect is aggravated. This is also much worse for EUV than for ArF or DUV because fewer photons are used for exposure. This is the dose contribution to LER. It is a natural variation in the exposure dose.
For chemically amplified resists, each photon ultimately generates lots of acids. The acid number has much less shot noise but at the cost of resolution (more blur), since these acids have to diffuse.
For ionizing radiation, as I mentioned elsewhere, each EUV or X-ray photon generates an avalanche of electrons which in turn can diffuse and generate more acids which also diffuse. These two factors increase blur significantly.
QUOTE
Such large uncertainty means one can have 2 nm pixels which are randomly unexposed.
I should say such large uncertainty means large variation of local exposure of 2 nm pixels.
QUOTE
ArF dose = 25 mJ/cm^2: 240 photons in a 2 nm square
This should be 960 photons (each being 6.425 eV in energy) in a 2 nm square. This gives 3s/avg = 3*sqrt(960)/960 = 10% shot dose variation in exposing a 2 nm pixel, assuming every incident 193 nm photon is absorbed.
The quantum efficiency of absorption also needs to be taken into account. If the QE is much less than 100%, that could make the 3s/avg much higher. If 3s/avg is close to 100%, then the exposure of a 2 nm pixel is almost randomly 'on' or 'off', giving a direct dose contribution to the roughness of the line edge on a 2 nm scale.
Checking the EUV calculation for the target dose of 5 mJ/cm^2:
5 mJ/cm^2 = 3.125 *10^16 eV/cm^2 = 312.5 eV/nm^2 = 3.4 92 eV photons/nm^2. Therefore, in a 2 nm square, there is ~14 EUV photons. This gives 3s/avg = 3*sqrt(14)/14 = 81%, which again gives a random 'on' or 'off' even at 100% quantum efficiency.
The number of photons absorbed is also a function of depth in the photoresist. Hence by the same argument, the shot noise roughness should be worse at the bottom of a photoresist trench or hole, since fewer photons make it there.
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You can get roughness just by developing straightforward PMMA e-beam resist. Of course chemically-amplified resists make things worse.
Polymer phase separation has been observed as a visible aspect of LER.
Aerial image quality is also important for e-beam lithography as proximity effects have been shown to aggravate LER.
Polymer phase separation has been observed as a visible aspect of LER.
Aerial image quality is also important for e-beam lithography as proximity effects have been shown to aggravate LER.
Plasma etching also worsens roughness in the masked material, after initially smoothing the photoresist. Very tricky stuff. 
QUOTE
Plasma etching also worsens roughness in the masked material, after initially smoothing the photoresist. Very tricky stuff.
I can see this happening if there are dense polymer aggregates in the photoresist which etch slightly slower than the rest of the photoresist. With longer etch time, this could result in a few nm difference.
Deep trench capacitors require larger and larger aspect ratios for smaller and smaller trenches. This will also impose some limits on lithography, at least for this DRAM technology.
Apparently unanswered question today: http://www.eetimes.com/news/semi/showArtic...cleID=180204904
QUOTE
The number of photons absorbed is also a function of depth in the photoresist. Hence by the same argument, the shot noise roughness should be worse at the bottom of a photoresist trench or hole, since fewer photons make it there.
Largest dose to size in literature is 36.8 mJ/cm^2. That's 25 photons/nm^2. 125 nm photoresist thickness. Apply the exponential attenuation. You see the picture.
The mean free path of an electron with Fermi energy of 7 eV in copper is ~39 nm.
http://hyperphysics.phy-astr.gsu.edu/hbase.../ohmmic.html#c2
What does that mean? It seems awfully a long distance (expecting a few nm or so).
http://hyperphysics.phy-astr.gsu.edu/hbase.../ohmmic.html#c2
What does that mean? It seems awfully a long distance (expecting a few nm or so).
QUOTE
The mean free path of an electron with Fermi energy of 7 eV in copper is ~39 nm.
http://hyperphysics.phy-astr.gsu.edu/hbase.../ohmmic.html#c2
What does that mean? It seems awfully a long distance (expecting a few nm or so).
http://hyperphysics.phy-astr.gsu.edu/hbase.../ohmmic.html#c2
What does that mean? It seems awfully a long distance (expecting a few nm or so).
The related links at that site give additional info. The mean free path is long because there is very little electron scattering into states close to the Fermi level. The electric field probably gives micro-eV energy difference. This is already smaller than thermal excitation (~0.026 eV at room temperature).
Impact ionization (which generates secondary electrons from primary ones) involves energy differences at least on the order of the Fermi energy, so for metals, the mean free path is small, but for insulators, where the density of states is much less, the mean free path is also large (observed to be > 10-20 nm).
McCord and Pease, JVST B vol. 6, p. 293-296 (1988).
Apparently 20 eV electrons from an STM can go through 20 nm PMMA.
Apparently 20 eV electrons from an STM can go through 20 nm PMMA.
http://www.cs.vu.nl/~nsilvis/microeng.pdf
Figure 3 shows spread of secondary-electron driven contamination growth. 20 nm spread at the surface is already visible.
Figure 3 shows spread of secondary-electron driven contamination growth. 20 nm spread at the surface is already visible.
http://scitation.aip.org/getabs/servlet/Ge...=cvips&gifs=Yes
More data from X-ray exposure on gold substrate.
The electrons seemed to move 50 nm from the resist-substrate interface into the resist.
These are mostly the secondary electrons (<10 eV) which have longest mean free path as well.
More data from X-ray exposure on gold substrate.
The electrons seemed to move 50 nm from the resist-substrate interface into the resist.
These are mostly the secondary electrons (<10 eV) which have longest mean free path as well.
QUOTE (John Larkin+Aug 23 2004, 07:21 PM)
Or just admit that something in the 40 nm range is as far as ICs are
going to go, Moore's Law has at last hit the wall, and who needs 100
billion transistors on a chip anyhow?
John
You dont want a really powerful computer that can design an engine that never knocks or breaks down. If you hit the wall you're going to get hurt John.
going to go, Moore's Law has at last hit the wall, and who needs 100
billion transistors on a chip anyhow?
John
You dont want a really powerful computer that can design an engine that never knocks or breaks down. If you hit the wall you're going to get hurt John.
Has anyone thought of going 3-D?......We now have the technology for 3-D printing why not apply it to processors?...although cooling these buggers will need a little imagination.
3D technology already being used through chip stacking. Maybe it's a cheat but definitely more transistors per unit area.
http://www.reed-electronics.com/electronic.../CA6351743.html
QUOTE
ASML Holding NV has debuted what it says is the chip industry's most advanced lithography system, the ASML TWINSCAN XT:1900i, set to ship in mid-2007.
In combination with low k1 capabilities, ASML said that its new next-generation 193nm immersion lithography system extends optical lithography for volume production to 40nm and below. The company added that the system delivers a new industry numerical aperture (NA) benchmark of 1.35, the near practical limit for water-based immersion technology...
...the XT:1900i will specifically enable volume production for logic devices down to 32nm and memory devices at 40nm and below...
In combination with low k1 capabilities, ASML said that its new next-generation 193nm immersion lithography system extends optical lithography for volume production to 40nm and below. The company added that the system delivers a new industry numerical aperture (NA) benchmark of 1.35, the near practical limit for water-based immersion technology...
...the XT:1900i will specifically enable volume production for logic devices down to 32nm and memory devices at 40nm and below...
QUOTE
ASML Holding NV has debuted what it says is the chip industry's most advanced lithography system, the ASML TWINSCAN XT:1900i, set to ship in mid-2007.
In combination with low k1 capabilities, ASML said that its new next-generation 193nm immersion lithography system extends optical lithography for volume production to 40nm and below. The company added that the system delivers a new industry numerical aperture (NA) benchmark of 1.35, the near practical limit for water-based immersion technology...
...the XT:1900i will specifically enable volume production for logic devices down to 32nm and memory devices at 40nm and below...
In combination with low k1 capabilities, ASML said that its new next-generation 193nm immersion lithography system extends optical lithography for volume production to 40nm and below. The company added that the system delivers a new industry numerical aperture (NA) benchmark of 1.35, the near practical limit for water-based immersion technology...
...the XT:1900i will specifically enable volume production for logic devices down to 32nm and memory devices at 40nm and below...
Obviously ASML wants to score as much revenue as possible from this tool.
game over.
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