Dielectric Etching Damage

plasma_guy

6th May 2008 - 11:36 AM

http://www.mrs.org/s_mrs/bin.asp?CID=2727&...01&DOC=FILE.PDF]

Low-k dielectric etching damage has been observed to be as extensive as 100 nm deep from the edge.

DavidD

8th May 2008 - 05:24 PM

I wonder what is dialectric thicness in current procesors? 100 nm?

plasma_guy

9th May 2008 - 04:12 AM

QUOTE

I wonder what is dialectric thicness in current procesors? 100 nm?

Less, maybe 70-80 nm at worst. But the dielectric currently used may is not as porous as the MSQ in the linked example.

It is getting there though, as porosity is expected to increase.

guiding_light

9th May 2008 - 04:48 AM

Many materials are prone to damage by etching, such as low-k dielectrics and ferroelectric materials. These materials, if absolutely necessary, probably should not be etched but deposited, but that would open up other questions and issues. For example, the dual-damascene process flow would have to be overturned possibly.

But interconnect RC delay is only increasing as pitch decreases, roughly proportional to inverse squared pitch. That should be considered the most fundamental limiter to blind scaling.

plasma_guy

9th May 2008 - 06:18 AM

QUOTE (guiding_light+May 9 2008, 04:48 AM)

Many materials are prone to damage by etching, such as low-k dielectrics and ferroelectric materials. These materials, if absolutely necessary, probably should not be etched but deposited, but that would open up other questions and issues. For example, the dual-damascene process flow would have to be overturned possibly.

Also need to consider metal oxidation during dielectric etching.

QUOTE (guiding_light+May 9 2008, 04:48 AM)

But interconnect RC delay is only increasing as pitch decreases, roughly proportional to inverse squared pitch. That should be considered the most fundamental limiter to blind scaling.

Yes that's true.

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