Conductive Layer On Resist For Stm

guiding_light

3rd May 2007 - 04:22 AM

Jpn. J. Appl. Phys. Vol. 41 (2002) L667-L668

Nanometer-Scale Surface Modification Using Scanning Tunneling Microscope (STM)-Based Lithography with Conductive Layer on Resist

Kenichi Ohtsuka and Kenji Yonei

Abstract:
The resolution on electron-beam lithography is limited by the electron scattering to high-energy incident electron. The field emission of scanning tunneling microscope (STM)-tip is used for having a very-minute electron-beam. STM electron-beam lithography can do by the low energy of the tunnel current between STMTip and flat electrode, that is formed by three layers that are from an electric conductor, a resist and a semiconductor substrate. We obtain the line of width 82 nm and depth 11 nm by a creative method uses the conductive layer in STM-based lithography.

Apparently several eV can go through more than 10 nm resist.

PhysOrg scientific forums are totally dedicated to science, physics, and technology. Besides topical forums such as nanotechnology, quantum physics, silicon and III-V technology, applied physics, materials, space and others, you can also join our news and publications discussions. We also provide an off-topic forum category. If you need specific help on a scientific problem or have a question related to physics or technology, visit the PhysOrg Forums. Here you’ll find experts from various fields online every day.