This DRAM layout looks pretty neat except it looks like the bit line contact looks really close to the nearest word line, possibly touching (i.e., the upper right arm of the 'X' touches WL1).
The other potential touching point is the node capacitor and the word line or bit line, although there is probably more vertical separation in this case.
In any case, even if not touching, there is the danger of leakage from bit line to word line through the dielectric in between, right? It has to be just few nm at most.