holoman
8th February 2006 - 03:12 PM
Guest
8th February 2006 - 03:59 PM
MRAM is only mentioned since NEC worked with Toshiba only on MRAM. However, Toshiba also developed the FeRAM as well. The second link is definitely more information. Thanks!
evanh
12th February 2006 - 03:44 AM
Both articles are meaningless without the datawidth specified.
The SDA article also provides a snippet of the datasheet where the cycletime of 34 ns is listed. That's already better that DRAM, almost twice as good as the compared FeRAM and that's on 240 nm transistors, so they are defintely closing in on the target of SRAM speed. Btw: The objective is CPU fabrication not mass storage.
The FeRAM technique is interesting in that it seems to require two memory banks, one of DRAM for fast access and one of Flash for snap-shotting the DRAM on power down. This is not likely to be a hit in the general computing market but is obviously atractive to comsumer items like cellphones, DVRs and in-car infotainment systems to replace the Flash/HDD and remove the horrid boot up times that has unnecessarily grown over the years.
Evan