Hi

Look here http://www.physorg.com/news52.htm

Seems that 65 nm technology is already not a problem if they plan to begin the initial production from it!!!

There are no physical limitations for 65nm technology anymore, I believe.
I only wonder about the current yield .

And what about gate dielectric then???? Isn't it a limitation? This problem isn't solved yet!

I just read three interesting papers:

"A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45 nm Gate Length Strained Silicon CMOS Transistors" (T. Ghani et. al., IEDM 2002)

"A 65 nm Logic Technology Featuring 35 nm Gate lengths, Enhanced Channel Strain, 8 Cu Interconnect Layers, Low K ILD, and 0.57 um^2 SRAM Cell" (P. Bai et. al., IEDM 2004)

"A 65 nm UltraLow Power Logic Platform Technology using Uni-axial Strained Silicon Transistors" (C-H Jan et. al, IEDM 2005).

There is no problem in going from 90 nm to 65 nm because the two process sets do not differ dramatically. It seems there was no need to change the process tools. Still, some things hardly changed at all, like the minimum pitch, which stayed above 200 nm. This is really loose compared to, say DRAM or flash memory.

I can think of only two reasons. One is copper resistivity (gets worse below 100 nm width). The other is not enough stressor material next to the gate.
This lessens the benefit of strained silicon.

Still, Intel managed to rearrange and/or shorten the features to pack them into a proportionally smaller cell. Looks like they did the same for 45 nm.