26th September 2009 - 05:10 PM
After Intel unveiled at IDF future projects, my own comments, half a penny worth. On architecture, not processes.
- Nice that they plan a dual-core processor with a faster clock. That's what I expect.
- Future vector hardware and instruction set: I'd ilke them to work on vectors of variable length and much longer than the computing unit, so that the instruction set doesn't change at all when future processors integrate wider computing units.
- Functional parallelism: maybe each unit (addresses computation, Load/Store, integer, float... May have several of each type) can have its own L1 cache holding only the instruction of the corresponding type, and tell the sequencer "I have everything to go to cycle number thatmuch" or "to loop count thatmuch", and the sequencer would only decide "Then, everybody goes to cycle thatmuch". Still compatible with i86, with a more parallel decision path and more instruction bandwidth.
- High parallelism in loops would be easier with instructions that configure the hardware, in a remnant way, before ticking just a loop counter. Like "This address will increment by 4" and "the accumulator must take its input from the multiplier" and "The counter must decrement and compare to zero". We can still define several kinds of ticks that command different groups of recently defined actions, for flexibility.
[No more compatible with i86, sorry. I think OpenGL works like this.]
- There, I propose to compress executable code a bit in order to accept less throughput and capacity from hard disks, Ram, maybe L2:http://www.msfn.org/board/index.php?showtopic=129474
The code would be moderately compact but very easy to expand so that on-chip additional hardware would decode it at full speed with no added latency. If the corresponding hardware works for instance at L2 speed, then only L1 stores expanded code.
Compressing at 3:2 only the code (not the data) would save up to one Ram access bus, maybe 1/5th of L3 and L2's size, and 1/5th of hard disk slowness.